Article 514EQ SMIC Details Its N+1 Process Technology: 7nm Performance in China

SMIC Details Its N+1 Process Technology: 7nm Performance in China

by
Anton Shilov
from on (#514EQ)

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SMIC first started volume production of chips using its 14 nm FinFET fabrication process in Q4 2019. Since then, the company has been hard at work developing its next generation major node, which it's calling N+1. The technology has certain features that are comparable to competing 7 nm process technologies, but SMIC wants to make it clear that N+1 is not a 7 nm technology.

When compared to SMIC's 14 nm process technology, N+1 lowers power consumption by 57%, increases performance by 20%, and reduces logic area by up to 63%. While the process enables chip designers to make their SoCs smaller and more power efficient, its modest performance gains do not allow N+1 to compete against competitors' 7 nm technology and derivatives. To that end, SMIC positions its N+1 as a technology for inexpensive chips.

A SMIC's spokesperson said the following:

"Our target for N+1 is low-cost applications, which can reduce costs by about 10 percent relative to 7nm. So this is a very special application."

Notably, SMIC's N+1 does not use extreme ultraviolet lithography (EUVL), so the fab company does not need to procure further expensive equipment from ASML. Which isn't to say that the company hasn't considered EUV - the company did acquire an EUV step-and-scan system - but it has not been installed, reportedly because of restrictions imposed by the US. As a result, it will be SMIC's N+2 that will use EUV.

The foundry from China plans to start risk production using its N+1 technology in Q4 2020, so expect the process to enter high volume manufacturing (HVM) sometimes in 2021 or 2022.

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Sources: SMIC, EE Times China

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