Researchers Tune HPC Codes for Intel Xeon Phi at Brookhaven Hackathon

"The goal of this hands-on workshop was to help participants optimize their application codes to exploit the different levels of parallelism and memory hierarchies in the Xeon Phi architecture," said CSI computational scientist Meifeng Lin. "By the end of the hackathon, the participants had not only made their codes run more efficiently on Xeon Phi-based systems, but also learned about strategies that could be applied to other CPU-based systems to improve code performance."

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