[$] Detecting and handling split locks

The Intel architecture allows misaligned memory access in situationswhere other architectures (such as ARM or RISC-V) do not. One suchsituation is atomic operations on memory that is split across two cachelines. This feature is largely unknown, but its impact is even less so. Itturns out that the performance and security impact can be significant,breaking realtime applications or allowing a rogue application to slow thesystem as a whole. Recently, Fenghua Yu has been working on detecting andfixing these issues in the split-lockpatch set, which is currently on its eighth revision.