Are You Ready for Your Next DDR Design
by Keysight from IEEE Spectrum on (#5RZDE)
With DDR getting into the multi-gigabit range, we see memory systems adopting high-speed serial technologies. New memory devices are using equalization (e.g. DDR5) and/or multi-level modulations (e.g. DDR6X and GDDR7 with PAM4).
As a result, designing with DDR becomes more challenging than ever before and standard signal integrity analysis is no longer sufficient.
Register for this free webinar now.
As you need to regenerate your signal from a closed data eye-diagram due to the channel effects, Keysight is offering a design flow, which lets you:
- Create and use JEDEC conform IBIS AMI models for DRAM drivers and receivers and easily connect them to the memory bus
- Get full understanding of the channel characteristics through end-to-end simulations
- Evaluate the design performance and margins of your DDR5 interface with IBIS-AMI modeling features such as Decision Feedback Equalization (DFE) and jitter tracking