Intel's Take on the Next Wave of Moore's Law

The next wave of Moore's Law will rely on a developing concept called system technology co-optimization, Ann B. Kelleher, general manager of technology development at Intel told IEEE Spectrum in an interview ahead of her plenary talk at the 2022 IEEE Electron Device Meeting. From a report: "Moore's Law is about increasing the integration of functions," says Kelleher. "As we look forward into the next 10 to 20 years, there's a pipeline full of innovation" that will continue the cadence of improved products every two years. That path includes the usual continued improvements in semiconductor processes and design, but system technology co-optimization (STCO) will make the biggest difference. Kelleher calls it an "outside-in" manner of development. It starts with the workload a product needs to support and its software, then works down to system architecture, then what type of silicon must be within a package, and finally down to the semiconductor manufacturing process. "With system technology co-optimization, it means all the pieces are optimized together so that you're getting your best answer for the end product," she says. STCO is an option now in large part because advanced packaging, such as 3D integration, is allowing the high-bandwidth connection of chiplets -- small, functional chips -- inside a single package. This means that what would once be functions on a single chip can be disaggregated onto dedicated chiplets, which can each then be made using the most optimal semiconductor process technology. For example, Kelleher points out in her plenary that high-performance computing demands a large amount of cache memory per processor core, but chipmaker's ability to shrink SRAM is not proceeding at the same pace as the scaling down of logic. So it makes sense to build SRAM caches and compute cores as separate chiplets using different process technology and then stitch them together using 3D integration. A key example of STCO in action, says Kelleher, is the Ponte Vecchio processor at the heart of the Aurora supercomputer. It's composed of 47 active chiplets (as well as 8 blanks for thermal conduction). These are stitched together using both advanced horizontal connections (2.5 packaging tech) and 3D stacking. "It brings together silicon from different fabs and enables them to come together so that the system is able to perform against the workload that it's designed for," she says.

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