CHERIoT 1.0 released

Version1.0 of the Capability Hardware Extension to RISC-V for IoT(CHERIoT) specification has been released. CHERIoT is ahardware-software system for secure embedded devices, and thespecification provides a full description of the ISA and its intendeduse by CHERIoTRTOS. David Chisnall has written a blogpost about the release that explains its significance as well as plansfor CHERIoT 2.0 and beyond:

The last change that we made to the ISA was in December 2024, so weare confident that this is a stable release that we can support inhardware for a long time. This specification was implemented by the1.0 release of CHERIoT Ibex and by CHERIoT Kudu (which has not yet hadan official release). These two implementations demonstrate that theISA scales from three-stage single-issue pipelines to six-stagedual-issue pipelines, roughly the same range of microarchitecturessupported by Arm's M profile.

We at SCI have the first of our ICENI chips, which use the CHERIoTIbex core, on the way back from the fab now and will be scaling up tomass production in the new year. I am not allowed to speak for otherfolks building CHERIoT silicon, but I expect 2026 to be an excitingyear for the CHERIoT project!