China's CXMT hits 12nm-class DRAM milestone — new 5th-gen DRAM tech uses quadruple-patterning to boost die capacity by 50%
China's DRAM champion CXMT has begun mass production using its 5th-generation DRAM process technology.
CXMT says its new process technology - G5, as the company calls it - reduces DRAM's active-area half-pitch to 11.95nm using quadruple-patterning lithography. The 11.95nm half-pitch corresponds to an active-area pitch of 23.9nm, something that puts this particular dimension roughly in the range of other advanced 10nm-class DRAM technologies. However, it cannot be directly translated into a conventional DRAM node designation. Separately, CXMT says its DRAM-optimized high-K metal gate (HKMG) process reduced the height of the core cell array to 6,762nm.
The company also says it modified its process flow and introduced unspecified new materials to enable storage capacitors with a depth-to-width aspect ratio of about 45:1.The figure is certainly difficult to compare directly with competing DRAM process technologies, but SK hynix says that capacitor aspect ratios will need to exceed 100:1 as DRAM critical dimensions eventually fall below 10nm.
A 45:1 aspect ratio means CXMT's storage capacitors are 45 times deeper than they are wide, which is what enables the company to reduce DRAM cell area and fit more memory arrays onto a wafer and retail predictable capacity. However, increasingly high aspect ratios make etching, deposition, mechanical stability, and ultimately high-yield manufacturing considerably more challenging.
The first disclosed mass-produced devices using G5 are said to be 24Gb LPDDR5X devices, which have already entered mass production. The chips offer 50% more capacity than CXMT's previous comparable products and are available in two package formats for different mobile-device designs. According to the Chinese report, the 24Gb LPDDR5X products are already entering mainstream Chinese flagship smartphones.
Meanwhile, there are some important caveats.
First up, CXMT's 11.95nm figure represents the active-area half-pitch rather than a conventional process-node designation, so calling G5 a 12nm process is a large degree of simplification at best.
Secondly, the two revealed physical dimensions do not mean technological parity with the latest DRAM processes from Micron, Samsung, and SK hynix, as density, capacitor scaling, transistor characteristics, power consumption, and, arguably most importantly when it comes to commodities, yields matter.
Thirdly, CXMT says G5 provides at least 50% more gross dies per wafer than G4, but without actual numbers, this is obsolete. CXMT also did not disclose yields, which makes it impossible to determine the increase in productivity, not to mention known-good dies or the actual manufacturing cost per bit. Yet again, even a claimed 11.95-class DRAM node is an achievement.