Gate Drive Measurement Considerations

One of the primary purposes of a gate driver is to enable power switches to turn on and off faster, improving rise and fall times. Faster switching enables higher efficiency and higher power density, reducing losses in the power stage associated with high slew rates. However, as slew rates increase, so do measurement and characterization uncertainty.

Effective measurement and characterization considerations must account for: a- Proper gate driver design - Accurate timing (propagation delay in regard to skew, PWD, jitter) - Controllable gate rise and fall times - Robustness against noise sources (input glitches and CMTI) a- Minimized noise coupling a- Minimized parasitic inductance

The trend for silicon based power designs over wide bandgap power designs makes measurement and characterization a greater challenge. High slew rates in SiC and GaN devices present designers with hazards such as large overshoots and ringing, and potentially large unwanted voltage transients that can cause spurious switching of the MOSFETs.