SPI Chip Select timing
by RogueWarrior65 from LinuxQuestions.org on (#5B244)
I'm working with the SPI interface and using the SPIDEV driver to talk to an ADC device. This device requires a one-byte write and a two-byte read. It can handle a clock speed of 1.8 MHz and a sample rate of 100 ksps.
It works but it's running very slowly. I've connected a logic analyzer to the system and I can see that the system is wasting a lot of time between SPI transactions where the chip select line is held low.
At the start of the transaction, it sets the chip select line for about 20 microseconds before the system starts clocking out the write data. After it reads the two response bytes, it wastes about 65 microseconds before resetting the chip select line. Basically, no matter what I do, the transaction always seems to take ~100 microseconds thus cutting my ADC sampling rate by a factor of 10.
Is this a driver issue or a kernel SPI code issue or what?
Does anyone know where in the kernel code the chip select timing is being set?
100 microseconds seems like a pretty specific value.
It works but it's running very slowly. I've connected a logic analyzer to the system and I can see that the system is wasting a lot of time between SPI transactions where the chip select line is held low.
At the start of the transaction, it sets the chip select line for about 20 microseconds before the system starts clocking out the write data. After it reads the two response bytes, it wastes about 65 microseconds before resetting the chip select line. Basically, no matter what I do, the transaction always seems to take ~100 microseconds thus cutting my ADC sampling rate by a factor of 10.
Is this a driver issue or a kernel SPI code issue or what?
Does anyone know where in the kernel code the chip select timing is being set?
100 microseconds seems like a pretty specific value.