CPU speeds, Bus Bandwidth, & similar stuff.

Back in the early days, you always had 4+ stages per cpu cycle

1. Address (for upcoming instruction)
2. Read Instruction
3. Compute (= internally decode) Instruction
4. Write Output

Now some instructions went to >=5 clock cycles and if you had one of the crappy things with Adress & data bus combined, they got much longer, but mostly the cpu speed was crystal/4. All cpu i/o chips were on this single Address & Data Bus.

Now in these days of multiple cores, caches, You lose track a bit. Take this example: https://www.solid-run.com/arm-server...b-workstation/
That has 16Core A-72 Arm Cores @2Ghz. For networking, they are imho vastly overspecified. They offer

• 1*100Gbps nic or 4*25Gbps nics
• Also 4*10Gbps nics

I looked at this and it didn't add up. Now they've a set of 2 DIMMs so maybe it's 8 cores each, but still it didn't seem to compute. I sent some searching questions.I got a reply back on the state of software progress, and a link to their software forum. It's definitely a Software WIP. A 10Gbps nic is only doing 2.5Gbps unless they use a 'passthrough IOMMU' in which case it's 6.5-7Gbps. They're telling me they'll get more cores talking to the nics, but haven't done the software yet.

• Sure it's got 16 Cores, but how much use are they?
• Could that thing ever keep a 100GB Nic at top whack?
• what on earth is going on instead of the single buses of old?
• What sort of bus bandwidth do you need to feed a 100Gb (10 GigaBytes per second) NIC?
• How does the IOMMU become the bottleneck?

EDIT: Just Found this: https://www.solid-run.com/arm-server...b-workstation/