Article 5H5S9 Astera Labs and Avery Design Partner on CXL 2.0 Verification for Smart Retimer Portfolio

Astera Labs and Avery Design Partner on CXL 2.0 Verification for Smart Retimer Portfolio

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from High-Performance Computing News Analysis | insideHPC on (#5H5S9)

Tewksbury, MA., April 28, 2021 - Avery Design Systems, a functional verification solutions company, today announced that Astera Labs, a connectivity solutions for intelligent systems specialist, successfully used Avery's Compute Express Link (CXL) 2.0 and PCI Express (PCIe) 5.0 Verification IP (VIP) and services in developing its Aries Smart Retimer portfolio. The Avery CXL 2.0 and PCIe [...]

The post Astera Labs and Avery Design Partner on CXL 2.0 Verification for Smart Retimer Portfolio appeared first on insideHPC.

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