Article 5RYMF Astera Labs Claims 1st CXL 2.0 Memory Accelerator SoC Platform

Astera Labs Claims 1st CXL 2.0 Memory Accelerator SoC Platform

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from High-Performance Computing News Analysis | insideHPC on (#5RYMF)

SANTA CLARA, CA, U.S. - November 15, 2021 - Astera Labs, make of connectivity solutions for intelligent systems, today announced its new Leo Memory Accelerator Platform for Compute Express Link (CXL) 1.1/2.0 interconnects to enable disaggregated memory pooling and expansion for processors, workload accelerators, and smart I/O devices. Leo overcomes processor memory bandwidth bottlenecks and [...]

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