How to Speed Up LVS Verification
This is a sponsored article brought to you by Siemens.
Layout versus schematic (LVS) comparison is a crucial step in integrated circuit (IC) design verification, ensuring that the physical layout of the circuit matches its schematic representation. The primary goal of LVS is to verify the correctness and functionality of the design. Traditionally, LVS comparison is performed during signoff verification, where dedicated tools compare layout and schematic data to identify any inconsistencies or errors. However, uncovering errors at the signoff stage leads to time-consuming iterations that delay design closure and time to market. While early-stage LVS comparison could mitigate these issues, it often generates millions of error results due to the incomplete status of the design.
To address these challenges, we developed a shift-left methodology, allowing designers to perform LVS comparison earlier in the design flow. By incorporating LVS checks at earlier stages, design teams can catch errors sooner and reduce the number of iterations required during signoff. Let's take a deeper look at how a shift-left LVS verification approach can enhance designer productivity and accelerate verification.
The Calibre nmLVSTM Recon Compare solution introduces an intelligent shift-left process for fast and precise LVS comparison earlier in the design cycle. It automates the black boxing of incomplete blocks and facilitates automatic port mapping, allowing designers to achieve faster LVS iterations on early-stage designs.
Challenges of traditional LVS verificationIn the traditional LVS verification process, designers must verify the layout against its schematic representation to ensure that the final product functions as intended. Because all design blocks must be completed and ready for final comparison, verification teams wait until signoff stages to perform thorough checks. Any errors discovered during this late-stage LVS run can trigger additional verification iterations, leading to wasted time and resources. Designers are then caught in a cycle of re-running the LVS process each time a fix or update is implemented, resulting in a bottleneck during signoff.
Designers could run LVS compare earlier, although in the early stages of design many blocks are not yet finalized, making a comprehensive LVS comparison impractical. Running LVS on incomplete designs can generate millions of error messages, many of which are not actionable because they originate from the uncompleted portions of the layout. This overwhelming number of results makes it difficult to pinpoint actual design issues, rendering traditional LVS methods impractical for early-stage verification.
As shown in figure 1, the verification flow can be more complex when design blocks are completed at different times, driving multiple iterations of verification checks as each block is integrated into the overall layout.
Fig. 1: Design verification cycle with blocks at different levels of completion.
Implementing a shift-left methodology for LVS verification means performing layout vs. schematic comparisons earlier in the design cycle, before all blocks are finalized. To enable this, the flow must support flexibility in dealing with incomplete designs and allow for more targeted verification of critical blocks and connections.
One way to achieve this is through automation techniques like black boxing and port mapping. By abstracting the internal details of incomplete blocks while preserving their external connectivity information, the verification flow can be tailored to focus on interactions between completed and incomplete sections of the design. Automated port mapping, on the other hand, ensures that all external connections between layout and schematic are correctly aligned for accurate early-stage comparisons.
A new approach to early LVS verificationAn advanced methodology for early-stage LVS verification leverages these automated processes to accelerate the shift-left verification process. For instance, intelligent black boxing of incomplete blocks can significantly reduce the number of error results generated, making it easier for verification teams to identify actual connectivity issues between blocks.
The shift-left flow also benefits from the use of a powerful comparison engine that can analyze layout and schematic data quickly and efficiently, skipping unnecessary operations and calculations. This approach focuses on the hardest problems early in the flow, resulting in fewer errors discovered at the signoff stage and ultimately speeding up design closure.
The flows illustrated in figure 2 shows how this shift-left methodology streamlines the verification process by reducing unnecessary steps and focusing on critical design issues.
Fig. 2: The traditional full LVS flow with all steps (left) vs. the Calibre nmLVS Recon flow (right).
Adopting a shift-left methodology for LVS verification offers several key benefits to semiconductor design teams:
Early detection of errors: By performing LVS comparisons earlier in the design flow, errors can be identified and resolved before they become deeply embedded in the design. This proactive approach reduces the risk of costly rework and minimizes the number of iterations needed during signoff.
Accelerated design verification: Automating the comparison process streamlines design verification, allowing designers to identify and resolve issues efficiently, even when all blocks are not finalized. This leads to faster overall circuit verification and reduces the time and effort required for manual inspection.
Improved collaboration and debugging: With a centralized platform for verifying design correctness and sharing feedback, early-stage LVS verification promotes collaboration across design teams. Engineers can isolate issues more effectively and provide insights to their colleagues, enhancing overall design quality.
Increased design confidence: Ensuring alignment between layout and schematic representations from the early stages of design boosts confidence in the final product's correctness. By the time the design reaches signoff, most of the critical connectivity issues have already been resolved.
Real-world applicationsCalibre nmLVS Recon has demonstrated significant benefits in real design projects, including 10x runtime improvements and 3x lower memory requirements. A verification team at Marvell, for example, enhanced their LVS flow over the full design cycle using Calibre nmLVS SI, achieving faster verification times and improved efficiency.
ConclusionShifting LVS compare tasks earlier into the design flow offers significant benefits to IC design teams. Our novel approach to early top-level LVS comparison automates black boxing and port mapping so designers can perform comprehensive verification even when all blocks are not finalized. This accelerates design verification, improves collaboration, and enhances design confidence in semiconductor design workflows.
Learn more by downloading my recent technical paper Accelerate design verification with Calibre nmLVS Recon Compare."