Why Thermal Metrology Must Evolve for Next-Generation Semiconductors

An in-depth examination of how rising power density, 3D integration, and novel materials are outpacing legacy thermal measurement - and what advanced metrology must deliver.

What Attendees will Learn

1. Why heat is now the dominant constraint on semiconductor scaling - Explore how heterogeneous integration, 3D stacking, and AI-driven power density have shifted the primary bottleneck from lithography to thermal management, with heat flux projections exceeding 1,000 W/cm^2 for next-generation accelerators.
2. How extreme material properties are redefining thermal design requirements -Understand the measurement challenges posed by nanoscale thin films where bulk assumptions fail, engineered ultra-high-conductivity materials (diamond, BAs, BNNTs), and devices operating above 200 C in wide-band gap systems.
3. Why interfaces and buried layers now govern reliability - Examine how thermal boundary resistance at bonded interfaces, TIM layers, and dielectric stacks has become a first-order reliability accelerator.
4. What a thermal-first design workflow looks like in practice - Learn how measured, scale-appropriate thermal properties can be integrated early in the design cycle to calibrate models, reduce uncertainty, and prevent costly late-stage failures across advanced packaging and 3D architectures.