Samsung Foundry updates process roadmap to move 1.4nm node to 2029 — high-NA EUV will enable 1nm-class and smaller nodes in 2030 and beyond
Samsung Foundry presented its updated fabrication technologies roadmap at the 2026 Next-Generation Lithography + Patterning Conference (NGL 2026) this week, revealing some major changes compared to the 2024 roadmap, reports ZDNet Korea. Instead of rushing its SF1.4 node (1.4nm-class) to the market, Samsung will focus on refining its SF2 (2nm-class) manufacturing processes in the next three years. And starting with its SF1A (1nm-class) fabrication node, Samsung intends to adopt High-NA EUV lithography tools, the first time the company confirms the plan.
Before moving on to 10-angstrom (or 1nm-class) node around 2030, Samsung will refine its SF2-series manufacturing technologies (which includes SF2P, SF2X, SF2A, and SF2Z with backside power delivery) and introduce its SF1.4 process in 2029.
The delay of SF1.4 from 2027 to 2029 indicates that the company is slowing its leading-edge cadence to focus resources on making its SF2 family more commercially competitive from yields and volumes point of view. Keeping in mind that Samsung has signed a long-term supply agreement with Tesla to supply AI5 and AI6 processors through 2033, the company's priority is to ensure that its major customer is happy.
Another reason for a long SF2 lifespan is the company's reported plan to finally adopt pellicles for EUV photomasks, which changes the usual routines at Samsung and likely forces it to reconsider process recipes for some of its future nodes.
Interestingly, but Samsung's 1nm-class node is said to co-exist with SF1.4+, an enhanced version of SF1.4 that uses an unusual nomenclature for Samsung. Such an approach indicates that the company will have both an "innovative" 1nm-class process that uses High-NA EUV lithography and a technology that relies on proven Low-NA EUV flows and materials.
Although Samsung has purchased an ASML Twinscan EXE:5000 EUV lithography scanner with 0.55 numerical aperture projection optics and has been using it for research purposes for well over a year, the company is not in any rush to adopt High-NA EUV lithography for its 2nm-class and 1.4nm-class fabrication technologies. Samsung only plans to insert such a tool for its 1nm-class process sometime in 2030.
"We wanted to apply High-NA EUV to mass production at nodes such as 2nm and 1.4nm, but the technology still requires further improvements," said Chang Min Park, Master VP of Technology at Samsung Electronics, at the conference. "We believe High-NA EUV will become necessary from A10 and below, and we are conducting joint development with various partners."
For chipmakers, the main challenge with ASML's High-NA EUV tools are substantially higher costs compared to Low-NA EUV systems used today, which greatly increases costs of fabs and can affect costs of chips. Meanwhile, High-NA EUV scanners introduce a smaller exposure field, which can require die stitching for large chips and complicate designs, which largely diminish their performance advantage over regular Low-NA EUV systems that stems on reducing the need for using multipatterning.
In addition, High-NA EUV needs improved photoresists, different masks, pellicles, metrology, inspection, and computational lithography, just to name some of the requirements. As a result, chipmakers must determine when it makes sense for them to use expensive single-patterning on High-NA EUV tools and when they can live with increasingly mature 0.33-NA EUV multi-patterning. For example, Intel intends use High-NA EUV tools with some of its 14A technologies, whereas TSMC looks at High-NA EUV lithography as on technology for the 2030s.