Smallest All-Digital Circuit Opens Doors to 5 nm Next-Gen Semiconductor
Arthur T Knackerbracket has found the following story:
Scientists at Tokyo Institute of Technology (Tokyo Tech) and Socionext Inc. have designed the world's smallest all-digital phase-locked loop (PLL). PLLs are critical clocking circuits in virtually all digital applications, and reducing their size and improving their performance is a necessary step to enabling the development of next-generation technologies.
[...] The entire all-digital PLL fits in a 50 i- 72 I1/4m2 region, making it the smallest PLL to date.
A core building block of SoC devices is the phase-locked loop (PLL), a circuit that synchronizes with the frequency of a reference oscillation and outputs a signal with the same or higher frequency.
PLLs generate 'clocking signals', whose oscillations act as a metronome that provides a precise timing reference for the harmonious operation of digital devices.
[...] Manufacturers have been racing to develop increasingly smaller semiconductors. 7 nm semiconductors (a massive improvement over their 10 nm predecessor) are already in production, and methods to build 5 nm ones are now being looked at.
However, in this endeavor stands a major bottleneck. Existing PLLs require analog components, which are generally bulky and have designs that are difficult to scale down.
Scientists at Tokyo Tech and Socionext Inc., led by Prof. Kenichi Okada, have addressed this issue by implementing a 'synthesizable' fractional-N PLL, which only requires digital logic gates, and no bulky analog components, making it easy to adopt in conventional miniaturized integrated circuits.
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