Corsair Explains DDR5 Memory

takyon writes:

Corsair's DDR5 primer has me dreaming of running 1TB of RAM

Corsair has put together a DDR5 primer (PDF) that discusses the next-gen RAM standard and what to expect. The biggest thing is an increase in bandwidth. The burst length, or how many bits of data can be read per cycle, has been doubled on DDR5 to 16 bits. That equates to 32 bits per channel and a full cache line of 64 bits total per module, for double data rate (DDR) memory.

[...] Corsair is also hoping to put latency concerns to bed. DDR5 kits have higher CAS latencies compared to DDR4, but according to Corsair, this is offset by DDR5's design, and specifically by splitting modules into two separate channels to allow for shorter traces.

"Individual modules are split into two separate channels by design, allowing for shorter traces that contribute to less latency and higher speeds when it comes to communicating with individual memory ICs on a memory module. This also allows for what's referred to as command/address mirroring since the signal from the CPU has to travel a shorter overall path to access specific banks of memory whereas in DDR4 a command/address signal had to travel through all banks of memory in a longer chain," Corsair explains.

DDR4 is different, in that whenever there is a need to refresh a single memory bank, the CPU sits there and waits for all memory banks to be refreshed before reading or writing from RAM. So even though the CAS latency of a DDR5 kit is higher than DDR4, the overall latency of a higher performing kit will be similar.

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