OpenPOWER Foundation | Libre-SOC 180nm Power ISA ASIC Submitted to Imec for Fabrication
upstart writes:
OpenPOWER Foundation | Libre-SOC 180nm Power ISA ASIC Submitted to Imec for Fabrication:
Libre-SOCs 180nm Power ISA Test ASIC, developed in conjunction with Chips4Makers and Sorbonne Universite's LIP6, has been submitted to Imec's MPW Shuttle Service for fabrication in TSMC 180nm.
The team that collaborated on the project has a wealth of expertise in software engineering and ethical hardware design, and as a matter of principle used a fully free and open source toolchain to deliver this groundbreaking chip. This makes it the first ASIC of its kind, with many more to come - each edging closer to an attractive open hardware alternative to current proprietary offerings. The project was funded by NLnet Foundation as part of its Next Generation Internet initiative, as a fundamental technological building block that will help increase privacy and trustworthiness for end users.
Implementing a fixed-point subset of the v3.0B OpenPOWER ISA, Libre-SOC's 180nm Power ISA Test ASIC is the world's first Power ISA implementation designed outside of IBM to go to silicon, following IBM's open sourcing of the POWER ISA in 2019. Libre-SOC used Microwatt, which was designed by IBM and sent to Skywater for fabrication earlier this year, as a reference design for benchmarking and cross-verification.
The ASIC is 130,000 gates, measures 5.5 x 5.9 mm^2, contains four 4k SRAMs developed by Chips4Makers, and a 300 mhz Voltage-Controlled PLL developed by Professor Galayko of Sorbonne Universite. The VLSI tape-out was carried out by Jean-Paul Chaput of Sorbonne Universite using coriolis2, and the Static Timing Analysis and LVS checking by Dr. Marie-Minerve Louerat of Sorbonne Universite. The HDL of the core is entirely in nmigen, a python Object-Orientated HDL.
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