Article 5RP55 AMD Announces Milan-X Epyc With 3D V-Cache, Bergamo, and First MCM GPU: Instinct MI200

AMD Announces Milan-X Epyc With 3D V-Cache, Bergamo, and First MCM GPU: Instinct MI200

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janrinok
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takyon writes:

AMD has announced its "Milan-X" Epyc CPUs, which reuse the same Zen 3 chiplets found in "Milan" Epyc CPUs with up to 64 cores, but with triple the L3 cache using stacked "3D V-Cache" technology designed in partnership with TSMC. This means that some Epyc CPUs will go from having 256 MiB of L3 cache to a whopping 768 MiB (804 MiB of cache when including L1 and L2 cache). 2-socket servers using Milan-X can have over 1.5 gigabytes of L3 cache. The huge amount of additional cache results in average performance gains in "targeted workloads" of around 50% according to AMD. Microsoft found an 80% improvement in some workloads (e.g. computational fluid dynamics) due to the increase in effective memory bandwidth.

AMD's next-generation of Instinct high-performance computing GPUs will use a multi-chip module (MCM) design, essentially chiplets for GPUs. The Instinct MI250X includes two "CDNA 2" dies for a total of 220 compute units, compared to 120 compute units for the previous MI100 monolithic GPU. Performance is roughly doubled (FP32 Vector/Matrix, FP16 Matrix, INT8 Matrix), quadrupled (FP64 Vector), or octupled (FP64 Matrix). VRAM has been quadrupled to 128 GB of High Bandwidth Memory. Power consumption of the world's first MCM GPU will be high, as it has a 560 Watt TDP.

The Frontier exascale supercomputer will use both Epyc CPUs and Instinct MI200 GPUs.

AMD officially confirmed that upcoming Zen 4 "Genoa" Epyc CPUs made on a TSMC "5nm" node will have up to 96 cores. AMD also announced "Bergamo", a 128-core "Zen 4c" Epyc variant, with the 'c' indicating "cloud-optimized". This is a denser, more power-efficient version of Zen 4 with a smaller cache. According to a recent leak, Zen 4c chiplets will have 16 cores instead of 8, will retain hyperthreading, and will be used in future Zen 5 Ryzen desktop CPUs as AMD's answer to Intel's Alder Lake heterogeneous ("big.LITTLE") x86 microarchitecture.

Also at Tom's Hardware (Milan-X).

Previously: AMD Reveals 'Instinct' for Machine Intelligence
AMD Launches "Milan" Epyc Server CPUs, with Zen 3 and up to 64 Cores
AMD at Computex 2021: 5000G APUs, 6000M Mobile GPUs, FidelityFX Super Resolution, and 3D Chiplets
AMD Unveils New Ryzen V-Cache Details at HotChips 33
AMD Aims to Increase Energy Efficiency of Epyc CPUs and Instinct AI Accelerators 30x by 2025

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