Arm And Risc-V: Can There Only Be One?
janrinok writes:
Most see these two as a winner-take-all, zero-sum contest:
In almost every discussion about RISC-V's position in the ecosystem, the instruction set architecture (ISA) is often seen as a direct competitor to Arm. Most people view the two ISAs as being engaged in a winner-take-all, zero-sum contest, where only one can prevail. However, we believe that, at least for the foreseeable future, the industry will witness a greater degree of mixing and matching. Both ISAs are likely to coexist side by side within increasingly heterogeneous chips.
Admittedly, the entire history of technology is against us on this one. Over the past 40 years, we have seen a recurring pattern: software ecosystems tend to consolidate around a single platform. No one wants to write the same software twice, and not just write but design, test, and debug. So, developers have generally followed their own paths to maximize profits, which, over time, leads to the dominance of a single platform.
However, this old truism is not entirely accurate... ISAs are not exactly software.
[...] Arm cores are largely fixed in their capabilities, whereas RISC-V cores are marketed as being very 'flexible' (though not entirely, but close enough for our discussion). By mixing and matching the two systems, chip designers can find more optimal paths for their needs.
This is not just theory; we have seen it in practice. Apple's A- and M-Series processors, as well as Google's TPUs, appear to incorporate both Arm and RISC-V cores. This trend is evident in many other chips as well.
[...] Will this remain the case forever? Ask anyone on either side, and they are quick to say no. Highlander rules apply, there can be only one. However, in practice, we are not so certain. Chips are changing, becoming more diverse and heterogeneous, as designers search for ways to cope with the slowing of Moore's Law. This has opened up the door to a rethinking of past rules. Therefore, we expect that for a long time to come, we will see both RISC-V and Arm sitting next to each other in many chips.
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