TSMC Lifts the Curtain on Nanosheet Transistors and Intel Shows How Far These Devices Could Go
taylorvich writes:
https://spectrum.ieee.org/tsmc-n2
TSMC described its next generation transistor technology this week at the IEEE International Electron Device Meeting (IEDM) in San Francisco. The N2, or 2-nanometer, technology is the semiconductor foundry giant's first foray into a new transistor architecture, called nanosheet or gate-all-around.
Samsung has a process for manufacturing similar devices, and both Intel and TSMC expect to be producing them in 2025.
Compared to TSMC's most advanced process today, N3 (3-nanometer), the new technology offers up to a 15 percent speed up or as much as 30 percent better energy efficiency, while increasing density by 15 percent.
N2 is "the fruit of more than four years of labor," Geoffrey Yeap, TSMC vice president of R&D and advanced technology told engineers at IEDM. Today's transistor, the FinFET, has a vertical fin of silicon at its heart. Nanosheet or gate-all-around transistors have a stack of narrow ribbons of silicon instead.
The difference not only provides better control of the flow of current through the device, it also allows engineers to produce a larger variety of devices, by making wider or narrower nanosheets. FinFETs could only provide that variety by multiplying the number of fins in a device-such as a device with one or two or three fins. But nanosheets give designers the option of gradations in between those, such as the equivalent of 1.5 fins or whatever might suit a particular logic circuit better.
Called Nanoflex, TSMC's tech allows different logic cells built with different nanosheetwidths on the same chip. Logic cells made from narrow devices might make up general logic on the chip, while those with broader nanosheets, capable of driving more current and switching faster, would make up the CPU cores.
The nanosheet's flexibility has a particularly large impact on SRAM, a processor's main on-chip memory. For several generations, this key circuit, made up of 6 transistors, has not been shrinking as fast as other logic. But N2 seems to have broken this streak of scaling stagnation, resulting in what Yeap described as the densest SRAM cell so far: 38 megabits per square millimeter, or an 11 percent boost over the previous technology, N3. N3 only managed a 6 percent boost over its own predecessor. "SRAM harvests the intrinsic gain of going to gate-all-around," says Yeap.
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