How We Added Interlaced Video to Raspberry Pi 5

Freeman writes:

https://www.raspberrypi.com/news/how-we-added-interlaced-video-to-raspberry-pi-5/

The very first Raspberry Pi had a composite video output, and all models with a 40-pin header have a display parallel interface (DPI) output. With some external components, DPI can be converted to VGA or RGB/SCART video. Those analogue interfaces are still in demand for retro media and gaming.

Raspberry Pi 5 was a big step up in processing power, but unlike previous models, its DPI block didn't support interlaced video (which isn't really part of the DPI standard), so it couldn't send full-resolution RGB to a CRT television. Until now.

To generate interlaced video, we had to do three things:

1. Get DPI to emit fields (even or odd lines of a frame-buffer) instead of frames
2. Time those signals so they will be in the proper arrangement for interlace
3. Generate appropriate sync pulses

The first part is easy. By changing an address and doubling the 'stride' between lines, we can arrange for DPI to read and display just the even or odd lines of a frame-buffer.

The second problem is solved by hacking the DPI peripheral. If we time it just right, we can change its configuration on the fly, so that every second frame - every second field, I should say - gets one extra blank line at the end.

The third problem is harder. RP1's DPI has no way to make vertical sync pulses start midway through a line.

Our RP1 chip has a Programmable Input/Output (PIO) block. We recently added PIO support to our version of the Linux kernel

Here, PIO snoops on DPI's horizontal sync (HSync) and data enable (DE) pins to generate vertical sync (VSync). Two of PIO's four state machines (SMs) are used: one SM serves as a timer, generating an 'interrupt' at the start and middle of each line. The other SM finds the start of the vertical blanking interval (the first line without DE), then counts half-lines to work out when to start and end the VSync pulse. Finally, it samples DE again to detect the extra blank line, to ensure it has the correct field-phase for next time.

The sync fixup consumes most of RP1's PIO instruction memory, so PIO can't be used for other cool things at the same time as generating interlaced DPI.

If you have a Raspberry Pi 5, a VGA666 HAT, and a VGA monitor that can run at 50Hz TV rates, you could test it by adding this to config.txt:

dtoverlay=vc4-kms-dpi-generic
dtparam=clock-frequency=13500000
dtparam=hactive=720,hfp=12,hsync=64,hbp=68
dtparam=vactive=576,vfp=5,vsync=5,vbp=39
dtparam=vsync-invert,hsync-invert
dtparam=interlaced

Composite sync too

VGA cables have separate wires for horizontal and vertical sync, but TVs combine everything in one signal (composite video). A halfway house, used in SCART, is 'composite sync', which multiplexes the two sync signals but keeps them separate from RGB.

RP1's DPI can't generate VSync in interlaced modes. Instead, we get it to output a 'helper signal' that alternates between 1-line and 2-line pulses. PIO snoops on HSync and the helper signal to synthesize CSync.

Original Submission

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