ASML Launches Revolutionary Lithography Scanner for Advanced 3D Chip Packaging
upstart writes:
ASML launches revolutionary lithography scanner for advanced 3D chip packaging:
Last week, ASML introduced the Twinscan XT:260 lithography scanner, the industry's first scanner that has been designed from the ground up for advanced 3D packaging, marking a new era in fab tools.
Advanced packaging technologies like TSMC's Chip-on-Wafer-on-Substrate (CoWoS) are crucially important to achieve the performance scaling necessary to develop artificial intelligence and to evolve supercomputers.
Advanced packaging relies on deposition, etching, lithography, and metrology/inspection tools to make sophisticated chips. But while using these front-end tools is efficient for many steps, they are overengineered for some, and insufficient for others.
"In line with our plans to support our customers in the 3D integration space, we shipped ASML's first product serving Advanced Packaging, the Twinscan XT:260, an i-line scanner offering up to 4x productivity compared to existing solutions.", ASML posted in its Q3 2025 financial results.
ASML's Twinscan XT:260 is an i-line (365 nm) step-and-scan lithography system that processes 300-mm wafers and weds the precision of previous-generation front-end lithography tools with the productivity and flexibility of back-end tools. TSMC claims this provides four times higher productivity compared to 'competing steppers' used for advanced packaging technologies, such as Canon's FPA-5520iV. ASML never named the exact competing product, but Canon's FPA-5520iV is a good bet.
The key advantage of the tool compared to some of the existing machines used for advanced packaging is that it supports a high-dose exposures (340 mJ is mentioned, though it is usually tunable) and a 52 mm * 66 mm image field, enabling the tool to process up to 3,432 mm^2 interposers (4X EUV reticle size) without field stitching, which reduces complexity and speeds up the production cycle. For the sake of truth, it should be noted that Canon's FPA-5520iV LF2 Option supports a 52 mm * 68 mm image field, but this is a stepper, not a scanner.
The system delivers 400 nm resolution, a 35 nm overlay, and offers a large depth of focus (11 m at 1 m CD) to enable accurate patterning for redistribution layers (RDLs) through-silicon vias (TSVs), and hybrid bonding structures used by modern packaging methods to integrate multi-chiplet designs. The unit also boasts 775 m through-silicon alignment capabilities to make it particularly suited for bonded or non-planar wafers, which are common in 3D stacking.
The Twinscan XT:260 relies on ASML's dual-stage platform, so it can expose one wafer while simultaneously aligning the next, which significantly increases its performance. Speaking of performance, the machine can process up to 270 wafers per hour (at a 340 mJ dose) and handle thick (0.775 mm - 1.7 mm) or warped (1 mm) wafers.
With a 400 nm resolution, 35 nm overlay, and the ability to handle thick or warped wafers (up to 1.7 mm), the XT:260 is optimized for technologies Intel's Foveros, TSMC's CoWoS and System-on-Integrated-Chips (SoIC), as well as other high-density die-stacking or interposer technologies which require precise alignment through silicon.
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