Researchers work out how to control 2D semiconductor growth for future chips

Researchers have demonstrated a way to control where 2D semiconductor crystals begin growing, potentially addressing an obstacle to manufacturing next-generation chips at scale, according to a study published in Nature. The paper, "Spatially deterministic nucleation of 2D semiconductors by etching flux," was authored by a team including researchers at KAIST and South Korean startup TDS Innovation and published on October 7. The technique uses an etching flux to suppress the formation of new crystals everywhere within each patterned growth region except at its geometric center. Two-dimensional materials are atomically thin rather than literally two-dimensional. Graphene, perhaps the best-known example, is a single layer of carbon atoms, but its lack of an intrinsic band gap makes it unsuitable for conventional switching transistors. Monolayers of some transition-metal dichalcogenides (TMDs), such as molybdenum disulfide (MoS), do have a band gap and are being investigated as materials for future transistors and other nanoscale devices. When grown on a wafer, however, 2D semiconductor crystals typically start forming at random points, or "nucleation events occur stochastically at random sites within the growth region," as the paper puts it. This means that multiple crystals form, and as they grow and meet, they create boundaries between them that degrade electrical performance and make devices less uniform. To encourage a single crystal to form in each patterned region, the researchers developed what they call an etching-flux-mediated single-centred nucleation (EF-SCN) process. Oxygen released from an oxide barrier creates a lateral etching flux that suppresses nucleation except at the pattern's geometric center. The researchers used the process to build working field-effect transistors (FETs), the basic building blocks of modern chips. They reported higher charge-carrier mobility - a measure of how readily charge moves through the material - than previously reported for selectively grown MoS transistors. In a separate test across a two-centimeter substrate, the process produced single crystals at 397 of 400 patterned sites - a yield of 99.3 percent. That is promising for scaling up, although it is not yet a demonstration of commercial chip production. Paper co-author Kibum Kang is co-CEO of TDS Innovation, which develops equipment and materials for 2D semiconductor devices. The firm says stacking 2D semiconductor devices on silicon chips could bring logic and memory closer together, fitting more functions into a given area and reducing the time and energy spent moving data between them. Two-dimensional semiconductor materials are also being investigated for CFETs (complementary field-effect transistors), which stack n-type and p-type transistors vertically rather than placing them side by side. This kind of 3D stacking has been shown off by IBM and Intel. "Building on this ability to control where crystal growth begins, we will form high-quality 2D single crystals uniformly where we want them and develop it into a next-generation semiconductor process that brings logic and memory closer together," Kang states. The paper doesn't say when we can expect to see 2D semiconductors made this way in production chips, TDS's Jony Jung told us: "We are aiming to enable commercial use of 2D semiconductors around 2030. We believe accelerating demand from AI, including physical AI and robotics, could help bring adoption forward, although production timing will depend on further validation." (R)