A closer look at Verano, AMD's first step toward a Zen-based superchip to rival Nvidia's Vera Rubin

AMD's upcoming Verano processors aren't like any Epyc CPUs we've seen before. Rather than general-purpose workloads, Verano is designed specifically to power AMD's next generation of GPU servers.

In an interview with The Register during a press event in Las Vegas last week, Madhu Rangarajan, CVP of AMD's compute and enterprise AI products business, described Verano as being the first step towards building something that more closely resembles Nvidia's Vera Rubin superchips.

"Verano is really designed for an integrated CPU+GPU rack scale solution," he said. "From that perspective, I wouldn't say the CPU is a competitor to Vera. In a head note, I'd say the Verano+GPU solution is a competitor to Vera+Rubin."

For reference, Vera Rubin and the GB200 and GB300 that came before it aren't your typical server platforms. Instead they're more like an enormous single-board computer combining CPUs and GPUs into a tightly-integrated package. Each of Nvidia's superchips joins a single 88-core Vera CPU and 1.5 TB of LPDDR5X memory to a pair of Rubin GPUs via Nvidia's speedy NVLink-C2C interconnect.

Rangarajan tells us Verano will be the host CPU for a similar class of product using AMD GPUs, and much like Nvidia's superchips, the CPU will also use notebook memory rather than conventional RDIMMS.

However, unlike Vera, which is also being deployed as a standalone CPU in storage servers and agent sandboxes, Verano has a singular purpose: keeping its GPUs fed. (We assume they'll be MI500X GPUs.)

This design choice reflects AMD's philosophy of one SKU per workload. As such, Verano's core count, clock speeds, memory bandwidth, power, and I/O have been rebalanced to keep its GPUs fed and not much else.

Under the hood

If we were to peel back Verano's heat spreader, the chip looks a lot like the Venice Epycs we looked at back in September. It features either six of AMD's core complex dies (CCDs) for a total of 72 high-frequency cores clocking to 5.3 GHz, or 192 density-optimized cores clocking to 4.1 GHz, depending on whether the customer's workloads prefer core density or faster clocks.

But that's about where the visual similarities end. Much of the chip has been reworked to eliminate data flow bottlenecks between the CPU and the GPUs it is responsible for feeding. The chip features an entirely custom pair of I/O dies through which four LPDDR5X memory controllers are attached.

Those memory controllers are currently being validated for use with 24 channels of memory at up to 8,533 MT/s. We're told that we may see that creep up a bit depending on how much headroom AMD has when the part starts shipping next year, but for now that's what AMD is validating against.

That means the platform not only has fewer cores, but also slower memory. Peak theoretical memory bandwidth tops out at around 800 GB/s, which you might have noticed is half of what AMD's top-specced Venice parts can do and about 66 percent of Nvidia's Vera.

What LPDDR seems to buy AMD is a 30 to 40 percent reduction in power consumption compared to RDIMMS, as well as a more compact footprint for liquid cooling. But it also comes with some downsides. In its first incarnation, Verano won't be socketed. Instead it'll use a ball-grid array (BGA) that's soldered to the board, which will make it harder to service.

"LPDDR tends to be quite finicky in terms of speeds. Every time you go through a connector, you tend to lose a pin or two, and you already have one connector with the SoCam itself. So to minimize any of those losses in speed, we went BGA on the CPU," Rangarajan told us.

Unlike with a lot of notebooks, the memory itself won't be soldered down and will use the same SOCAMM2 modules found in Nvidia's Vera-Rubin and Vera-Vera CPU Superchips.

Even so, Verano looks like a bit of a downgrade compared to Venice except when it comes to CPU-to-GPU connectivity.

Fatter pipes

Historically, AMD's CPU-to-GPU communication has been done over PCIe. It works but has usually required PCIe switches to keep up with all the GPUs, NICs, and storage on board. Nvidia's superchip dispensed with this, replacing PCIe with its NVLink-C2C interconnect, which provides 900 GB/s of bidirectional bandwidth to each of the system's GPUs.

Venice and Verano do something similar. Unlike past Instinct accelerators, AMD's latest generation of GPUs aren't limited to PCIe for CPU-to-GPU communication. Instead, starting with Venice, AMD transitioned to using xGMI.

Global memory interconnect (GMI) is how AMD has moved data between chiplets on its CPUs, GPUs, and APUs for several generations now. xGMI extends this to GPU-to-GPU and CPU-to-GPU communications.

With Venice, xGMI link bandwidth tops out at 64 Gbps per lane, which the keen-eyed among you have probably already figured out is the same as PCIe 6.0. Verano takes this to another level. As we mentioned earlier, Verano disaggregated the memory controllers, and AMD appears to have reclaimed that space for fatter Serializer/Deserializer (SerDes). Instead of 64 Gbps per lane, Verano's xGMI links top out at 112 Gbps, effectively giving it near PCIe 7.0 levels of bandwidth years before the spec ships in production CPUs.

Rangarajan explains this is driven by what AMD's GPUs need to run optimally.

AMD hasn't disclosed the ratio of CPUs to GPUs it's aiming for with Verano, so it's difficult to say how it compares to Nvidia. In a 2:1 ratio of GPUs to CPUs like we saw in Vera Rubin, Verano would deliver identical chip-to-chip bandwidth, while in a 1:4 ratio like we see in AMD's Helios racks, we'd be looking at about half the bandwidth at 448 GB/s. It's also not clear whether AMD has increased the number of xGMI links per I/O die for Verano or not, so bandwidth per GPU could be even higher. We expect more info closer to the MI500X's debut next year.

Part of a broader ecosystem

AMD doesn't expect Verano to replace Venice in every AI rack: The chip is designed specifically for use with Instinct accelerators. Moreover, AMD isn't waiting for Verano to roll out its Helios rackscale systems. As we discussed during Advancing AI earlier this year, those systems will feature 18 96-core Venice CPUs paired to 72 Instinct MI455X GPUs.

Moving forward, AMD expects its Venice to remain a popular host processor for AI head nodes not just for its own GPUs but for the growing number of homegrown accelerators built by the great model houses. (R)