New Intel, Toshiba SSD Technologies Squeeze More Bits Into Each Cell
Arthur T Knackerbracket has found the following story:
Wednesday, Intel announced it's joining Toshiba in the PLC (Penta-Level Cell, meaning 5 bits stored per individual NAND cell) club. Intel has not yet commercialized the technology, so you can't go and buy a PLC SSD yet-but we can expect the technology will lead eventually to higher-capacity and cheaper solid state drives.
Intel also differentiates itself from competitors by sticking with the floating-gate cell design used in early SLC devices, instead of the less expensive charge-trap design the rest of the industry has shifted to. It's unclear to casual researchers which technology is actually better from a technical perspective, but Intel argues that the floating gates can be manufactured at a higher density, meaning it can pack more cells into the same physical area.
Unfortunately, while PLC SSDs will likely be bigger and cheaper, they'll probably also be slower. Modern SSDs mostly use TLC storage with a small layer of SLC write cache. As long as you don't write too much data too fast, your SSD writes will seem as blazingly fast as your reads-for example, Samsung's consumer drives are rated for up to 520MB/sec. But that's only as long as you keep inside the relatively small SLC cache layer; once you've filled that and must write directly to the main media in real time, things slow down enormously.
[...] With sequential write speeds to QLC media already decreasing to or below that of conventional hard drives, PLC seems likely to be a niche player that will compete far more with NAS and datacenter drives than it does with laptop and desktop SSDs aimed at high performance. Sequential throughput isn't everything, of course-and PLC media should still offer much higher IOPS in challenging random-access workloads than conventional disks can. But it's probably not going to be a good solution in anything but truly massive-capacity drives, which can use higher parallelism (think "invisible RAID0") to offset the invididually-slow characteristics of PLC cells.
-- submitted from IRC
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