TSMC's Chip-on-Wafer-on-Substrate (CoWoS) Connects Multiple Interposers
takyon writes:
TSMC & Broadcom Develop 1,700 mm2 CoWoS Interposer: 2X Larger Than Reticles
TSMC and Broadcom have also been playing with the idea of oversized chips, and this week they've announced their plans to develop a supersized interposer to be used in Chip-on-Wafer-on-Substrate (CoWoS) packaging.
Overall, the proposed 1,700 mm^2 interposer is twice the size of TSMC's 858 mm^2 reticle limit. Of course, TSMC can't actually produce a single interposer this large all in one shot - that's what the reticle limit is all about - so instead the company is essentially stitching together multiple interposers, building them next to each other on a single wafer and then connecting them. The net result is that an oversized interposer can be made to function without violating reticle limits.
The new CoWoS platform will initially be used for a new processor from Broadcom for the HPC market, and will be made using TSMC's EUV-based 5 nm (N5) process technology. This system-in-package product features 'multiple' SoC dies as well as six HBM2 stacks with a total capacity of 96 GB. According to Broadcom's press release, the chip will have a total bandwidth of up to 2.7 TB/s, which is in line with what Samsung's latest HBM2E chips can offer.
Also at Guru3D.
Previously: TSMC Shows Off Gigantic Silicon Interposer
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