TSMC: Ecosystem For 2nm Chip Development Is Nearing Completion
Arthur T Knackerbracket has processed the following story:
Speaking to partners last week as part of their annual Open Innovation Platform forum in Europe, a big portion of TSMC's roadshow was dedicated to the next generation of the company's foundry technology. TSMC's 2 nm-classN2,N2P, and N2X process technologiesare set to introduce multiple innovations, including nanosheet gate-all-around (GAA) transistors, backside power delivery, and super-high-performance metal-insulator-metal (SHPMIM) capacitor over the next few years. But in order to take advantage of these innovations, TSMC warns, chip designers will need to use all-new electronic design automation (EDA), simulation, and verification tools as well as IP. And while making such a big shift is never an easy task, TSMC is bringing some good news to chip designers early-on: even with N2 still a couple of years out, many of the major EDA tools, verification tools, foundation IP, and even analog IP for N2 are already available for use.
[...] Preparations for the start of N2 chip production, scheduled for sometime in the second half of 2025, began long ago. Nanosheet GAA transistors behave differently than familiar FinFETs, so EDA and other tool and IP makers had to build their products from scratch. This is where TSMC's Open Innovation Platform (OIP) demonstrated its prowess and enabled TSMC's partners to start working on their products well in advance.
By now, major EDA tools from Cadence and Synopsys as well as many tools from Ansys and Siemens EDA have been certified by TSMC, so chip developers can already use them to design chips. Also, EDA software programs from Cadence and Synopsys are ready for analog design migration. Furthermore, Cadence's EDA tools already support N2P's backside power delivery network.
With pre-built IP designs, things are taking a bit longer. TSMC's foundation libraries and IP, including standard cells, GPIO/ESD, PLL, SRAM, and ROM are ready both for mobile and high-performance computing applications. Meanwhile, some PLLs exist in pre-silicon development kits, whereas others are silicon proven. Finally, blocks such as non-volatile memory, interface IP, and even chiplet IP are not yet available - bottlenecking some chip designs - but these blocks in active development or planned for development by companies like Alphawave, Cadence, Credo, eMemory, GUC, and Synopsys, according to a TSMC slide. Ultimately, the ecosystem of tools and libraries for designing 2 nm chips is coming together, but it's not all there quite yet.
[...] Although many of the major building blocks for chips are N2-ready, a lot of work still has to be done by many companies before TSMC's 2 nm-class process technologies go into mass production. Large companies, which tend to design (or co-design) IP and development tools themselves are already working on their 2 nm chips, and should be ready with their products by the time mass production starts in 2H 2025. Other players can also fire up their design engines because 2 nm preps are well underway at TSMC and its partners.
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