Intel CEO Claims 18A Node Will at Least Match TSMC's N2 Performance and Beat It to Market
Arthur T Knackerbracket has processed the following story:
Intel CEO Pat Gelsinger has claimed that its upcoming 18A process node (essentially 1.8nm) could outperform TSMC's 2nm chips despite launching a year earlier. The comments contradict recent claims from the Taiwanese competitor. Gelsinger made the remarks in an interview with Barrons.
[...] Additionally, TSMC is confident that its 2nm N2 node, slated for 2025, will outperform N3P and 18A. Following the company's inaugural 3nm process pattern, Apple could get first dibs on N2 and utilize it for the iPhone 17 Pro.
Much of Gelsinger's confidence in 20A and 18A lies in their introduction of the RibbonFET architecture - the company's take on gate-all-around (GAA) transistors and backside power delivery. These technologies will become crucial for companies manufacturing 2nm chips, enabling higher logic densities and clock speeds with reduced power leakage. Meanwhile, TSMC's N3P and other upcoming 3nm nodes will continue utilizing the mature FinFET architecture until it migrates to GAA with N2 a year after Intel.
Intel and TSMC aren't the only companies preparing to build 2nm semiconductors. Samsung also wants to enter 2nm mass production in 2025, while Japanese fabricator Rapidus plans to introduce prototypes by 2025, with mass production beginning in 2027.
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