Intel Has a Serious Problem With Arrow Lake and Memory Compatibility

upstart writes:

Intel has a serious problem with Arrow Lake and memory compatibility:

We've had Intel's Arrow Lake chips on the test benches lately, and the performance we were expecting wasn't quite there. Even on some of the best LGA1851 motherboards, we've noticed various performance quirks that need more than just a quick fix. One of those odd behaviors is DDR5 RAM sticks that refuse to boot at XMP settings, regardless of what speed they are rated for.

This is separate from the latency issue caused by the slower bus speed and the shifting of the memory controller to the SoC tile instead of on the compute tile, and it seems Arrow Lake is pickier with memory than any Intel platform I can think of since forever. I mean, Intel has always been the processor to get for using fast, low-latency RAM, and that long streak has now ended.

RAM compatibility for Arrow Lake is abysmal, Intel used to be the gold standard for fast RAM support but no longer

I've been around computing a long time, long enough that dual-data rate RAM wasn't even a thing at the time. Every new DDR revision has come with teething issues, as have most major CPU architecture changes. DDR5 still isn't a mature technology, but it's getting close as faster speeds combined with low timings are becoming more common. Arrow Lake is the first major architecture change from Intel since 2023's Alder Lake, when both DDR4 and DDR5 were supported.

Both of these new technologies seem to have caused more issues when combined, and this is one of the worst launches I've had hands-on experience with for memory compatibility. Arrow Lake feels pickier than even first-gen Ryzen was, back when Samsung B-die was the king for DDR4 RAM, spending hours looking over spec sheets and forums to find the memory kits using the vaunted DRAM modules.

But Ryzen at least had a common fix, as every Samsung B-die memory stick worked fine once the DDR and SoC voltages were increased slightly. When the Core Ultra 9 285 K was on the test bench, I tried nearly a dozen different DDR5 kits, and not one would boot with XMP enabled. Those kits ranged between 5,600MT/s and 8,800MT/s and between 16GB and 32GB per DIMM. Some of those kits were early DDR5 with XMP support, some were recent, and two kits were of the new CUDIMM variety that have an onboard clock driver to enable faster RAM speeds on Arrow Lake specifically. Some even had trouble booting at JEDEC speeds, which I've never experienced on any platform.

The only kit that did boot at higher speeds was from Kingston, and they were 8,800MT/s CUDIMMs. But it wasn't any of the BIOS settings I set from the years of RAM overclocking experience that I have on multiple platforms that worked. I had to boot into Windows and use Gigabyte's AI Snatch program, which tested the RAM and used algorithms to decide what speed and timings the kit should be using. After a reboot into BIOS to enable those AI generated settings and ensuring the DDR voltage was set to 1.45V, it booted into Windows at 8,933MT/s.

There was one last issue, however, in that the RAM would only run in Gear 4. Most low-latency memory DDR4 runs in Gear 1; using Gear 2 is a way to get higher speeds but at a slight penalty to latency, as it runs the memory at a 2:1 ratio compared to the memory controller. Most DDR5 uses Gear 2 to begin with, and to get higher speeds on Arrow Lake, drops to a 4:1 ratio, aka Gear 4. That's a huge performance hit in latency, on top of the considerable latency that Arrow Lake has by design. And remember, this is one kit out of nearly a dozen that could run at or above its rated speed.

XMP speeds will get fixed for the most part, as we've seen with AMD's Ryzen and how much better it handles RAM compatibility since its initial release. Arrow Lake is Intel's Ryzen moment, with the potential to do much more and build better CPUs in the future. It just has to get there, and the ring bus that shuttles data between the CPU and L3 cache and the hop to the memory controller are two things that need improving for the next silicon release. Intel can mitigate some of the aspects of the memory hit, but it can't do much about the inherent latency of the trip between the SoC tile and the compute tile.

It will likely involve a combination of silicon fixes, Windows, and driver improvements, as AMD did with Ryzen. If the computer's software is aware of the latency, it can be rewritten to account for it somewhat and make the system snappier as a result.

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